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৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১]

পরীক্ষা৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১]তারিখতারিখ অনির্ধারিতসময়30 minutes
মোট প্রশ্ন৪৬
সিলেবাস
Exam 14 Fundamentals of computer design; ALU and control design; Instruction cycle; pipelining; hazards; Cache memory; memory hierarchy; Systolic arrays; Fault tolerance; Bus and micro-programmed control. [Source: Class–12 and relevant books]
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৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১]

৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১] · তারিখ অনির্ধারিত · ৪৬ প্রশ্ন

১.
Which of the following best defines Computer Organization as distinct from Computer Architecture?
  1. ক
     Deals with how different units of a computer are interconnected and operate
  2. খ
    Specifies the instruction set and addressing modes visible to a programmer
  3. গ
    Describes the high-level algorithm design for system software
  4. ঘ
    Concerned only with I/O device specifications
ব্যাখ্যা

Answer: A
Explanation:
    Computer Architecture → Programmer’s view: instruction set, addressing modes, data types, registers.
    Computer Organization → How the architecture is implemented: control signals, data paths, memory hierarchy, I/O subsystems.
   For example, “ADD R1, R2, R3” belongs to architecture (visible instruction). The actual adder circuit, pipeline, and timing belong to organization.

২.
Which is the primary performance equation for CPU execution time?
  1. ক
    Execution Time = Instruction Count / Clock Rate
  2. খ
    Execution Time = Instruction Count × CPI × Clock Cycle Time
  3. গ
     Execution Time = MIPS × CPI
  4. ঘ
     Execution Time = Clock Rate × CPI
ব্যাখ্যা

Answer: B
Explanation:
CPU Time = Instruction Count (IC) × Cycles Per Instruction (CPI) × Clock Cycle Time.
    Instruction Count → depends on program + compiler.
    CPI → depends on instruction mix + microarchitecture.
    Clock cycle time = 1 / clock rate → depends on technology.
This equation is the foundation of computer performance analysis.

৩.
Which of the following trade-offs is not typical in computer design?
  1. ক
    Performance vs. Cost
  2. খ
     Power vs. Performance
  3. গ
    Flexibility vs. Efficiency
  4. ঘ
     Algorithm vs. Transistor count
ব্যাখ্যা

Answer: D
Explanation:
Designers constantly balance cost, power, efficiency, and performance.
Algorithm design is software domain;
transistor count is hardware domain.
Trade-off exists indirectly but is not a primary hardware design axis.

৪.
The primary performance metric in computer design, defined as “time to execute a given program,” is:
  1. ক
    Throughput
  2. খ
    Latency
  3. গ
    CPU Time
  4. ঘ
    CPI (Cycles Per Instruction)
ব্যাখ্যা

Answer: C
Explanation:
CPU Time = (Instruction count × CPI × Clock cycle time).
Latency is delay per operation,
throughput is operations per unit time,
CPI is a subcomponent.

৫.
Which of the following is a key advantage of pipelined processors?
  1. ক
    Decreases clock cycle time but increases CPI
  2. খ
     Allows multiple instructions to overlap in execution
  3. গ
    Reduces hardware cost significantly
  4. ঘ
    Eliminates all hazards automatically
ব্যাখ্যা

Answer: B
Explanation:
Pipelining increases throughput by overlapping instruction execution (fetch, decode, execute, memory, writeback). CPI ideally approaches 1. However, hazards (structural, data, control) must be managed.

৬.
Why is superscalar design different from pipelining?
  1. ক
    Superscalar executes multiple instructions per cycle, pipelining only overlaps stages
  2. খ
     Superscalar needs no hazard detection
  3. গ
    Superscalar only applies to RISC processors
  4. ঘ
    Both are identical
ব্যাখ্যা

Answer: A
Explanation:
    Pipelining = overlap stages, 1 instruction per cycle ideally.
    Superscalar = multiple pipelines → multiple instructions per cycle.
Hazards still exist and must be handled (instruction scheduling, renaming).

৭.
Why is instruction scheduling important in ALU pipelines?
  1. ক
    It reduces hardware cost
  2. খ
    It avoids stalls caused by hazards
  3. গ
    It increases CPI
  4. ঘ
    It simplifies compiler design
ব্যাখ্যা

Answer: B
Explanation:
Instruction scheduling reorders instructions to minimize stalls caused by hazards (e.g., placing independent instructions between dependent ones). This increases throughput without changing correctness.

৮.
The control unit in a CPU is responsible for:
  1. ক
    Performing arithmetic operations
  2. খ
    Fetching instructions from memory and generating control signals
  3. গ
    Storing program data
  4. ঘ
    Handling input/output transfers
ব্যাখ্যা

Answer: B
Explanation:
  → The control unit directs the operation of the processor.
   → t fetches instructions from memory, decodes them, and issues control signals to ALU, memory, and I/O units.
  → Arithmetic is done by ALU, and storage is handled by memory.

৯.
A hardwired control unit uses:
  1. ক
    ROM-based microinstructions
  2. খ
    Decoders and fixed combinational logic
  3. গ
    Software-level control
  4. ঘ
     Cache memory
ব্যাখ্যা

Answer: B
Explanation:
    Hardwired control is built from combinational logic circuits.
    It is very fast but difficult to modify.
    Microprogrammed control (option A) uses ROM to store control sequences

১০.
Which type of control unit is most suitable for RISC processors?
  1. ক
    Hardwired
  2. খ
    Microprogrammed
  3. গ
    Software-based
  4. ঘ
    Hybrid
ব্যাখ্যা

Answer: A
Explanation:

RISC → small, simple instruction set.
Hardwired control is fast and efficient for this.
CISC → complex instruction sets → better with microprogramming.

১১.
The main disadvantage of vertical microprogramming is:
  1. ক
    Very wide control word
  2. খ
    Difficulty in decoding encoded fields
  3. গ
    Inability to support parallelism
  4. ঘ
     High cost of ROM
ব্যাখ্যা

Answer: C
Explanation:
•    Vertical encoding saves memory by grouping control signals into fields.
•    But only one control signal per field can be active at once → limited parallelism.
Horizontal microprogramming avoids this limitation.

১২.
If control memory has 1024 microinstructions, each 48 bits wide, what is its size?
  1. ক
    48 KB
  2. খ
    6 KB
  3. গ
    8 KB
  4. ঘ
    12 KB
ব্যাখ্যা

Answer: B
Explanation:
Size = 1024 × 48 bits = 49,152 bits = 6144 bytes = 6 KB.

১৩.
The microinstruction cycle consists of:
  1. ক
     Fetch and Execute phases
  2. খ
     Fetch, Decode, Execute
  3. গ
    Fetch microinstruction, Generate control signals, Next address decision
  4. ঘ
     Instruction fetch and operand fetch
ব্যাখ্যা

Answer: C
Explanation:
•    In microprogrammed control:
1.    Fetch microinstruction from control memory
2.    Generate control signals to datapath
3.    Next address decision → go to next microinstruction or branch in microcode.

১৪.
Which of the following is a hybrid control approach?
  1. ক
     Combining hardwired logic for simple instructions and microprogramming for complex ones
  2. খ
    Using only horizontal microinstructions
  3. গ
    Running two microprograms simultaneously
  4. ঘ
    Implementing ALU and control unit together
ব্যাখ্যা

Answer: A
Explanation:
•    Many modern CPUs (e.g., x86) use hybrid control:
o    Common instructions (ADD, SUB) → hardwired for speed
o    Complex ones (string moves, floating point) → microprogrammed.

১৫.
Which of the following is true for RISC vs CISC control design?
  1. ক
    RISC → microprogrammed, CISC → hardwired
  2. খ
     RISC → hardwired, CISC → microprogrammed
  3. গ
    Both always microprogrammed
  4. ঘ
     Both always hardwired
ব্যাখ্যা

Answer: B
Explanation:
•    RISC → simple instruction set → easy to implement in hardwired control.
•    CISC → complex instructions → better suited for microprogramming

১৬.
The main bottleneck of microprogrammed control is:
  1. ক
    Instruction set complexity
  2. খ
    ALU hardware cost
  3. গ
    Microinstruction fetch from control memory
  4. ঘ
    Register file access
ব্যাখ্যা

Answer: C
Explanation:
Fetching microinstructions from control memory adds delay. That’s why microprogrammed units are slower compared to hardwired units.

১৭.
The primary motivation for using cache memory is:
  1. ক
    To increase memory capacity
  2. খ
    To reduce average memory access time
  3. গ
    To provide permanent storage
  4. ঘ
     To replace main memory
ব্যাখ্যা

Answer: B
Explanation:
Cache is a small, fast memory placed between CPU and main memory. It takes advantage of locality of reference (temporal + spatial) to reduce average access time. It does not increase capacity, nor is it permanent storage

১৮.
In a direct-mapped cache, each memory block:
  1. ক
    Can be placed only in one specific cache line
  2. খ
    Can be placed in any cache line
  3. গ
    Can be placed in multiple cache lines
  4. ঘ
    Cannot be cached
ব্যাখ্যা

Answer: A
Explanation:
Direct mapped = each block maps to exactly one line using Index = (Block number) mod (Number of lines).
•    Fully associative → any line.
•    Set-associative → small group of possible lines

১৯.
Which memory technology is used for cache memory?
  1. ক
    DRAM
  2. খ
    SRAM
  3. গ
    Flash
  4. ঘ
    EEPROM
ব্যাখ্যা

Answer: B
Explanation:
•    Cache → built from SRAM (Static RAM) → faster, no refresh required.
•    Main memory → DRAM (slower but denser).
•    Flash/EEPROM → non-volatile, for storage not cache

২০.
Which memory hierarchy level is Non-volatile?
  1. ক
    Cache
  2. খ
    Main memory (DRAM)
  3. গ
    Registers
  4. ঘ
    HDD
ব্যাখ্যা

Answer: D
Explanation:
Registers, cache, and main memory → volatile (lost on power-off).
Secondary storage (SSD, HDD, Flash) → non-volatile.

২১.
Virtual memory is:
  1. ক
    A technique to provide large storage using secondary memory
  2. খ
    A type of physical memory inside CPU
  3. গ
    A replacement for RAM
  4. ঘ
     A cache memory technique
ব্যাখ্যা

Answer: a) A technique to provide large storage using secondary memory 

Explanation:

Virtual memory is an OS technique where processes see a very large logical address space, even though physical RAM is smaller. It uses disk (secondary memory) + RAM + MMU (Memory Management Unit).

       (b) Virtual memory is not physical, it is logical.
       (c)  It does not replace RAM; it extends it using disk
       (d) Caching is a different concept (fast small memory between CPU and RAM).

২২.
Which hardware unit helps implement virtual memory?
  1. ক
    CPU registers
  2. খ
    Cache controller
  3. গ
    Memory Management Unit (MMU)
  4. ঘ
    Arithmetic Logic Unit (ALU)
ব্যাখ্যা

Answer: c) Memory Management Unit (MMU) 
Explanation:
    MMU translates virtual addresses → physical addresses using page tables.
    (a)  Registers are small fast memory inside CPU.
    (b)  Cache controller manages cache, not VM.
    (d)  ALU does arithmetic, not memory management

২৩.
What is the main advantage of virtual memory?
  1. ক
    Faster memory access
  2. খ
    Provides illusion of large memory using secondary storage
  3. গ
    Eliminates page faults
  4. ঘ
    Replaces cache
ব্যাখ্যা

Answer: B
Explanation:
Virtual memory allows programs to use more memory than physically available. It swaps pages between main memory and disk, providing illusion of large contiguous memory space.

২৪.
An Exception in computer architecture is best described as:
  1. ক
    An event that disrupts normal program flow, requiring special handling
  2. খ
    A hardware signal indicating normal program execution
  3. গ
    A form of permanent I/O device error
  4. ঘ
    A cache miss event
ব্যাখ্যা

Answer: A
Explanation:

Exceptions occur when unusual conditions arise (divide by zero, invalid opcode, page fault).
They interrupt normal instruction flow and transfer control to an exception handler.
Unlike cache misses, exceptions are system-level events.

২৫.
Which of the following is NOT a type of exception?
  1. ক
    Interrupt
  2. খ
    Trap
  3. গ
    Overflow
  4. ঘ
    Memory access alignment
ব্যাখ্যা


Answer: A
Explanation:
•    Interrupts are external events (I/O, timer).
•    Exceptions include traps, faults, aborts (internal to CPU).
•    Overflow, invalid memory alignment are exceptions.

২৬.
Which of the following best describes a trap Exception?
  1. ক
    Generated by hardware error
  2. খ
    Intentionally invoked by an instruction for debugging or system call
  3. গ
    Always fatal to the system
  4. ঘ
    Cannot be handled by OS
ব্যাখ্যা

Answer: B
Explanation:
•    Trap = synchronous, intentional exception (e.g., system call, breakpoints).
•    Faults = recoverable (e.g., page fault).
•    Aborts = unrecoverable (e.g., hardware failure).

২৭.
The table that stores exception handler addresses is called:
  1. ক
     Cache directory
  2. খ
    Page table
  3. গ
    TLB
  4. ঘ
    Interrupt vector table
ব্যাখ্যা

Answer: B
Explanation:

Interrupt/exception vector table maps exception numbers to handler addresses.
Page table maps virtual to physical memory.
TLB caches page table entries.

২৮.
Which of the following exceptions is synchronous?
  1. ক
    Keyboard interrupt
  2. খ
     Disk I/O completion
  3. গ
     Divide-by-zero
  4. ঘ
    Timer interrupt
ব্যাখ্যা

Answer: C
Explanation:
•    Synchronous: triggered by instruction execution (divide-by-zero, invalid opcode).
•    Asynchronous: triggered by external devices (I/O, timers).

২৯.
The term precise exception means:
  1. ক
    Exception always occurs at predictable cycles
  2. খ
    All previous instructions complete, and no later instructions are executed
  3. গ
    Exceptions can be reordered for performance
  4. ঘ
     Exception handling is only synchronous
ব্যাখ্যা

Answer: B
Explanation:
•    Precise exception → clear boundary: all earlier instructions finished, later instructions not executed.
•    Easier for OS to handle.
•    Out-of-order CPUs require mechanisms (like reorder buffers) to maintain precise exceptions.

৩০.
Which system component is mainly responsible for exception handling?
  1. ক
    ALU
  2. খ
    Cache
  3. গ
     Operating System
  4. ঘ
    DMA Controller
ব্যাখ্যা

Answer: C
Explanation:
•    OS handles exceptions by executing the appropriate handler routine.
•    Hardware only signals exception and passes control.

৩১.
If an exception occurs during another exception’s handling, this is called:
  1. ক
    Nested exception
  2. খ
     Masked exception
  3. গ
    Precise exception
  4. ঘ
     Non-recoverable exception
ব্যাখ্যা

Answer: A
Explanation:
•    Nested exception = exception while handler itself is running.
•    Some architectures support nesting, others only allow one at a time.

৩২.
A bus in computer organization is:
  1. ক
    A physical pathway for carrying only instructions
  2. খ
    A dedicated register for I/O devices
  3. গ
    A component that stores program counters
  4. ঘ
    A communication system that transfers data, addresses, and control signals
ব্যাখ্যা

Answer: D
Explanation:

A bus is a shared communication pathway.
It carries data lines (actual values), address lines (where to read/write), and control lines (read/write signals, clock, interrupts).
Unlike registers, buses are interconnection systems.

৩৩.
Which of the following is NOT a type of bus?
  1. ক
    Data bus
  2. খ
    Address bus
  3. গ
    Control bus
  4. ঘ
    Arithmetic bus
ব্যাখ্যা

Answer: D
Explanation:
•    Standard buses: data, address, control.
•    No “arithmetic bus” exists; arithmetic is done in the ALU.

৩৪.
In a synchronous bus, timing is coordinated by:
  1. ক
    Handshaking signals
  2. খ
    Clock signal
  3. গ
    Independent device timers
  4. ঘ
    Interrupt service routines
ব্যাখ্যা

Answer: B
Explanation:
•    Synchronous bus: all devices use a common clock to coordinate.
•    Asynchronous bus: uses handshaking signals (REQ/ACK)

৩৫.
Which of the following is a structural hazard?
  1. ক
     Two instructions needing the same functional unit simultaneously
  2. খ
    Branch instruction before the outcome is known
  3. গ
    Load followed immediately by dependent instruction
  4. ঘ
    Page fault
ব্যাখ্যা

Answer: A
Explanation:
•    Structural hazard: hardware resource conflict (e.g., single memory for instruction & data).
•    Control hazard: branches.
•    Data hazard: dependence between instructions.

৩৬.
Which technique is most effective for reducing data hazards?
  1. ক
     Prefetching
  2. খ
    Branch prediction
  3. গ
     Operand forwarding (bypassing)
  4. ঘ
    Cache coherence
ব্যাখ্যা

Answer: C
Explanation:
   Operand forwarding:  allows result of an instruction to be used immediately without waiting for it to be written back to register file.
   Prefetching helps with memory stalls, not data hazards

৩৭.
The main role of an I/O subsystem is:
  1. ক
    Execute arithmetic operations
  2. খ
    Connect and manage communication between CPU, memory, and peripherals
  3. গ
     Store programs permanently
  4. ঘ
    Speed up cache access
ব্যাখ্যা

Answer: B
Explanation:
The I/O subsystem acts as a bridge between CPU/memory and I/O devices (disk, keyboard, network). It manages data transfers, synchronization, buffering, and device control.

৩৮.
Which of the following is not an I/O technique?
  1. ক
    Programmed I/O
  2. খ
    Interrupt-driven I/O
  3. গ
     DMA (Direct Memory Access)
  4. ঘ
    Virtual memory paging
ব্যাখ্যা

Answer: D
Explanation:
•    Programmed I/O: CPU polls device until ready.
•    Interrupt-driven I/O: Device interrupts CPU when ready.
•    DMA: Transfers data directly between memory & device.
•    Virtual memory is memory management, not I/O.

৩৯.
The main disadvantage of programmed I/O is:
  1. ক
    Complex hardware
  2. খ
    High CPU involvement, leading to inefficiency
  3. গ
    Unreliable data transfer
  4. ঘ
     It cannot work with slow devices
ব্যাখ্যা

Answer: B
Explanation:
•    In programmed I/O, CPU continuously polls device → wastes cycles.
•    Not scalable for slow devices.
Interrupts and DMA reduce CPU burden

৪০.
Which of the following is TRUE about DMA (Direct Memory Access)?
  1. ক
    CPU handles every byte transferred
  2. খ
    DMA increases CPU execution time
  3. গ
    DMA is slower than programmed I/O
  4. ঘ
    DMA controller transfers data directly between memory and device
ব্যাখ্যা

Answer: D
Explanation:
•    DMA controller manages bulk transfers directly.
•    CPU only initializes DMA → no per-byte intervention.
•    This reduces CPU overhead and increases throughput.

৪১.
Which bus is typically used for connecting I/O devices in a computer system?
  1. ক
    Data bus only
  2. খ
     Instruction bus
  3. গ
    Arithmetic bus
  4. ঘ
    System bus / I/O bus
ব্যাখ্যা

Answer: D
Explanation:
I/O devices communicate via I/O bus (like PCIe, USB).
System bus is often split into data, address, and control buses

৪২.
In memory-mapped I/O, I/O devices:
  1. ক
    Have separate I/O instructions
  2. খ
    Share the same address space as memory
  3. গ
    Require no CPU intervention
  4. ঘ
     Cannot use DMA
ব্যাখ্যা

Answer: B
Explanation:

In memory-mapped I/O, part of the CPU’s address space is assigned to I/O devices.

That means the same read/write instructions used for RAM can also access device registers.

Example: If RAM occupies addresses 0x0000 – 0x7FFF, and device registers are mapped at 0x8000 – 0x8FFF, the CPU just loads/stores to those addresses.

Advantage: No need for special I/O instructions; programming is easier.

Disadvantage: Reduces available memory address space (some addresses are reserved for I/O).

৪৩.
Which device would most likely use interrupt-driven I/O instead of programmed I/O?
  1. ক
    Keyboard
  2. খ
     CPU registers
  3. গ
    Cache
  4. ঘ
    ALU
ব্যাখ্যা

Answer: A
Explanation:
•    Keyboard generates infrequent events.
•    Interrupt-driven I/O is ideal for low-bandwidth, asynchronous devices.

৪৪.
Which of the following is not a type of parallelism?
  1. ক
    Instruction-level parallelism
  2. খ
    Task-level parallelism
  3. গ
    Pipeline parallelism
  4. ঘ
    Cache coherence parallelism
ব্যাখ্যা

Answer: D
Explanation:
Types of parallelism:
1. Instruction-level, 
2. Data-level,
3. Task-level, pipeline.

Cache coherence is a consistency problem in multiprocessors, not a type of parallelism.

৪৫.
An interrupt is:
  1. ক
     A delay in cache access
  2. খ
     A signal to the CPU indicating an event that needs immediate attention
  3. গ
    A special instruction for pipelining
  4. ঘ
    A branch misprediction
ব্যাখ্যা

Answer: B
Explanation:
•    Interrupts allow CPU to temporarily halt current execution and service an event (I/O completion, timer, error).
•    After servicing, CPU resumes program.

৪৬.
A fault-tolerant computer primarily uses:
  1. ক
    Faster pipelines
  2. খ
     Redundancy to detect and correct errors
  3. গ
     Larger caches
  4. ঘ
    Parallel ALUs only
ব্যাখ্যা

Answer: B
Explanation:
•    Fault tolerance = system continues to operate despite hardware/software failures.
•    Techniques:
o    Triple Modular Redundancy (TMR)
o    ECC memory
o    Checkpoint & rollback
•    Essential in aerospace, banking, and safety-critical systems.