৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১]

Answer: A
Explanation:
    Computer Architecture → Programmer’s view: instruction set, addressing modes, data types, registers.
    Computer Organization → How the architecture is implemented: control signals, data paths, memory hierarchy, I/O subsystems.
   For example, “ADD R1, R2, R3” belongs to architecture (visible instruction). The actual adder circuit, pipeline, and timing belong to organization.

Answer: B
Explanation:
CPU Time = Instruction Count (IC) × Cycles Per Instruction (CPI) × Clock Cycle Time.
    Instruction Count → depends on program + compiler.
    CPI → depends on instruction mix + microarchitecture.
    Clock cycle time = 1 / clock rate → depends on technology.
This equation is the foundation of computer performance analysis.

Answer: D
Explanation:
Designers constantly balance cost, power, efficiency, and performance.
Algorithm design is software domain;
transistor count is hardware domain.
Trade-off exists indirectly but is not a primary hardware design axis.

Answer: C
Explanation:
CPU Time = (Instruction count × CPI × Clock cycle time).
Latency is delay per operation,
throughput is operations per unit time,
CPI is a subcomponent.

Answer: B
Explanation:
Pipelining increases throughput by overlapping instruction execution (fetch, decode, execute, memory, writeback). CPI ideally approaches 1. However, hazards (structural, data, control) must be managed.

Answer: A
Explanation:
    Pipelining = overlap stages, 1 instruction per cycle ideally.
    Superscalar = multiple pipelines → multiple instructions per cycle.
Hazards still exist and must be handled (instruction scheduling, renaming).

Answer: B
Explanation:
Instruction scheduling reorders instructions to minimize stalls caused by hazards (e.g., placing independent instructions between dependent ones). This increases throughput without changing correctness.

Answer: B
Explanation:
  → The control unit directs the operation of the processor.
   → t fetches instructions from memory, decodes them, and issues control signals to ALU, memory, and I/O units.
  → Arithmetic is done by ALU, and storage is handled by memory.

Answer: B
Explanation:
    Hardwired control is built from combinational logic circuits.
    It is very fast but difficult to modify.
    Microprogrammed control (option A) uses ROM to store control sequences

Answer: A
Explanation:

RISC → small, simple instruction set.
Hardwired control is fast and efficient for this.
CISC → complex instruction sets → better with microprogramming.

Answer: C
Explanation:
•    Vertical encoding saves memory by grouping control signals into fields.
•    But only one control signal per field can be active at once → limited parallelism.
Horizontal microprogramming avoids this limitation.

Answer: B
Explanation:
Size = 1024 × 48 bits = 49,152 bits = 6144 bytes = 6 KB.

Answer: C
Explanation:
•    In microprogrammed control:
1.    Fetch microinstruction from control memory
2.    Generate control signals to datapath
3.    Next address decision → go to next microinstruction or branch in microcode.

Answer: A
Explanation:
•    Many modern CPUs (e.g., x86) use hybrid control:
o    Common instructions (ADD, SUB) → hardwired for speed
o    Complex ones (string moves, floating point) → microprogrammed.

Answer: B
Explanation:
•    RISC → simple instruction set → easy to implement in hardwired control.
•    CISC → complex instructions → better suited for microprogramming

Answer: C
Explanation:
Fetching microinstructions from control memory adds delay. That’s why microprogrammed units are slower compared to hardwired units.

Answer: B
Explanation:
Cache is a small, fast memory placed between CPU and main memory. It takes advantage of locality of reference (temporal + spatial) to reduce average access time. It does not increase capacity, nor is it permanent storage

Answer: A
Explanation:
Direct mapped = each block maps to exactly one line using Index = (Block number) mod (Number of lines).
•    Fully associative → any line.
•    Set-associative → small group of possible lines

Answer: B
Explanation:
•    Cache → built from SRAM (Static RAM) → faster, no refresh required.
•    Main memory → DRAM (slower but denser).
•    Flash/EEPROM → non-volatile, for storage not cache

Answer: D
Explanation:
Registers, cache, and main memory → volatile (lost on power-off).
Secondary storage (SSD, HDD, Flash) → non-volatile.

Answer: a) A technique to provide large storage using secondary memory 

Explanation:

Virtual memory is an OS technique where processes see a very large logical address space, even though physical RAM is smaller. It uses disk (secondary memory) + RAM + MMU (Memory Management Unit).

       (b) Virtual memory is not physical, it is logical.
       (c)  It does not replace RAM; it extends it using disk
       (d) Caching is a different concept (fast small memory between CPU and RAM).

Answer: c) Memory Management Unit (MMU) 
Explanation:
    MMU translates virtual addresses → physical addresses using page tables.
    (a)  Registers are small fast memory inside CPU.
    (b)  Cache controller manages cache, not VM.
    (d)  ALU does arithmetic, not memory management

Answer: B
Explanation:
Virtual memory allows programs to use more memory than physically available. It swaps pages between main memory and disk, providing illusion of large contiguous memory space.

Answer: A
Explanation:

Exceptions occur when unusual conditions arise (divide by zero, invalid opcode, page fault).
They interrupt normal instruction flow and transfer control to an exception handler.
Unlike cache misses, exceptions are system-level events.

Answer: A
Explanation:
•    Interrupts are external events (I/O, timer).
•    Exceptions include traps, faults, aborts (internal to CPU).
•    Overflow, invalid memory alignment are exceptions.

Answer: B
Explanation:
•    Trap = synchronous, intentional exception (e.g., system call, breakpoints).
•    Faults = recoverable (e.g., page fault).
•    Aborts = unrecoverable (e.g., hardware failure).

Answer: B
Explanation:

Interrupt/exception vector table maps exception numbers to handler addresses.
Page table maps virtual to physical memory.
TLB caches page table entries.

Answer: C
Explanation:
•    Synchronous: triggered by instruction execution (divide-by-zero, invalid opcode).
•    Asynchronous: triggered by external devices (I/O, timers).

Answer: B
Explanation:
•    Precise exception → clear boundary: all earlier instructions finished, later instructions not executed.
•    Easier for OS to handle.
•    Out-of-order CPUs require mechanisms (like reorder buffers) to maintain precise exceptions.

Answer: C
Explanation:
•    OS handles exceptions by executing the appropriate handler routine.
•    Hardware only signals exception and passes control.

Answer: A
Explanation:
•    Nested exception = exception while handler itself is running.
•    Some architectures support nesting, others only allow one at a time.

Answer: D
Explanation:

A bus is a shared communication pathway.
It carries data lines (actual values), address lines (where to read/write), and control lines (read/write signals, clock, interrupts).
Unlike registers, buses are interconnection systems.

Answer: D
Explanation:
•    Standard buses: data, address, control.
•    No “arithmetic bus” exists; arithmetic is done in the ALU.

Answer: B
Explanation:
•    Synchronous bus: all devices use a common clock to coordinate.
•    Asynchronous bus: uses handshaking signals (REQ/ACK)

Answer: A
Explanation:
•    Structural hazard: hardware resource conflict (e.g., single memory for instruction & data).
•    Control hazard: branches.
•    Data hazard: dependence between instructions.

Answer: C
Explanation:
   Operand forwarding:  allows result of an instruction to be used immediately without waiting for it to be written back to register file.
   Prefetching helps with memory stalls, not data hazards

Answer: B
Explanation:
The I/O subsystem acts as a bridge between CPU/memory and I/O devices (disk, keyboard, network). It manages data transfers, synchronization, buffering, and device control.

Answer: D
Explanation:
•    Programmed I/O: CPU polls device until ready.
•    Interrupt-driven I/O: Device interrupts CPU when ready.
•    DMA: Transfers data directly between memory & device.
•    Virtual memory is memory management, not I/O.

Answer: B
Explanation:
•    In programmed I/O, CPU continuously polls device → wastes cycles.
•    Not scalable for slow devices.
Interrupts and DMA reduce CPU burden

Answer: D
Explanation:
•    DMA controller manages bulk transfers directly.
•    CPU only initializes DMA → no per-byte intervention.
•    This reduces CPU overhead and increases throughput.

Answer: D
Explanation:
I/O devices communicate via I/O bus (like PCIe, USB).
System bus is often split into data, address, and control buses

Answer: B
Explanation:

In memory-mapped I/O, part of the CPU’s address space is assigned to I/O devices.

That means the same read/write instructions used for RAM can also access device registers.

Example: If RAM occupies addresses 0x0000 – 0x7FFF, and device registers are mapped at 0x8000 – 0x8FFF, the CPU just loads/stores to those addresses.

Advantage: No need for special I/O instructions; programming is easier.

Disadvantage: Reduces available memory address space (some addresses are reserved for I/O).

Answer: A
Explanation:
•    Keyboard generates infrequent events.
•    Interrupt-driven I/O is ideal for low-bandwidth, asynchronous devices.

Answer: D
Explanation:
Types of parallelism:
1. Instruction-level, 
2. Data-level,
3. Task-level, pipeline.

Cache coherence is a consistency problem in multiprocessors, not a type of parallelism.

Answer: B
Explanation:
•    Interrupts allow CPU to temporarily halt current execution and service an event (I/O completion, timer, error).
•    After servicing, CPU resumes program.

Answer: B
Explanation:
•    Fault tolerance = system continues to operate despite hardware/software failures.
•    Techniques:
o    Triple Modular Redundancy (TMR)
o    ECC memory
o    Checkpoint & rollback
•    Essential in aerospace, banking, and safety-critical systems.