৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১]

Answer: a) The central integrated circuit that performs arithmetic, logic, and control functions

A microprocessor is essentially the CPU (Central Processing Unit) on a single chip.
It executes instructions from memory, performing:
→Arithmetic operations (via ALU)
→Logic operations (AND, OR, XOR, NOT)
→Control operations (fetch, decode, execute cycle)
It does not include memory or I/O devices (that’s part of a microcomputer or microcontroller).

Microprocessor = brains of computer.
Microcontroller = all-in-one embedded chip.

Answer: b) Intel 4004
Detailed Explanation:
    Intel 4004 (1971) = world’s first commercial microprocessor.
   Specs:
    4-bit processor
    2300 transistors
    Clock speed: 740 kHz
    Used in calculators and basic control systems
•    It was not powerful enough for general-purpose computing but revolutionized computer architecture.
Other options:
    a) 8086 (1978) → first 16-bit Intel processor, but not the first ever.
    c) Motorola 68000 (1979) → powerful 16/32-bit processor, but came later.
    d) Zilog Z80 (1976) → popular 8-bit processor, but not the first.
Key Point:
 Intel 4004 = first microprocessor (4-bit)
 Intel 8008, 8080, 8085 = 8-bit successors
 Intel 8086 = foundation of x86 architecture

Answer:  c) 4th (32-bit)
Explanation:
Pipelining = overlapping execution of instructions (fetch, decode, execute simultaneously).
It improves instruction throughput.
Introduced widely in 4th generation (32-bit processors, early 1980s).
Example: Intel 80386 (1985) → 32-bit microprocessor with advanced pipelining.

Other options:
1st gen (4-bit, 1971–73): No pipelining, very basic (Intel 4004).
2nd gen (8-bit, mid-1970s): Still sequential execution (Intel 8080, Z80).
5th gen (64-bit, 1990s): Used superscalar, RISC optimizations → but pipelining was already standard.

Answer:  d) Arithmetic Logic Unit (ALU)
Detailed Explanation:
    ALU is the heart of the processor’s data manipulation.
    Functions:
    Arithmetic (addition, subtraction, multiplication, division)
    Logic (AND, OR, NOT, XOR, shifts, rotations)
    Works directly with processor registers (AX, BX, etc. in 8086).
    Control unit issues control signals, ALU executes actual computation.

Other options:
    a) Control Unit → only directs operations, doesn’t compute.
    b) Instruction Register → just holds the current instruction.
    c) Bus Interface Unit → manages data flow between CPU and memory, not calculations.

Answer: c) Data Bus
Detailed Explanation:
    Data Bus:
    Carries the binary data (instructions or operands).
    Bidirectional → CPU can read (memory → CPU) or write (CPU → memory).
    Width of data bus = determines how many bits can be transferred simultaneously.
    8-bit bus → 1 byte at a time.
    16-bit bus → 2 bytes at a time.
Other options:
    a) Address Bus → carries the memory address (unidirectional).
    b) Control Bus → carries signals like Read/Write, Interrupt, Clock.
    d) Power Bus → not part of logical data transfer, only supplies voltage.
Key Point:
 → Address Bus = “Where?”
→ Data Bus = “What?”
 → Control Bus = “How?”

Answer:  b) 64 KB
Detailed Explanation:
    Address Bus width = number of unique memory locations.
    Formula:
                   Max Memory=2^{Address Bus Width} 
    If Address Bus = 16 bits →2¹⁶=65,536 bytes=64 KB
Other options:
    a) 16 KB → corresponds to 14-bit address bus.
    c) 1 MB → requires 20-bit address bus (8086).
    d) 4 GB → requires 32-bit address bus (80386

Answer:  a) The technique of specifying operands for instructions
Detailed Explanation:
  Addressing mode determines how the CPU accesses operands for instructions. It tells the CPU whether the operand is in a register, memory, or is an immediate value. Proper use of addressing modes improves flexibility and efficiency of programs.
    Operands can be:
        →Inside CPU registers
        →In memory locations
        →Part of the instruction itself
    Example:
    MOV AX, BX → Register mode
    MOV AX, 5000H → Immediate or direct depending on context

Answer: b) Register

Register Addressing Mode:

→ Operand is already in a CPU register.

→ CPU does not need to access memory.

→ Fetching data from a register takes 1 CPU cycle or very few cycles.

Example: MOV AX, BX → value in BX copied to AX.
In others Case: need to access memory. Memory access (direct, immediate, base+index) always adds extra cycles.

Answer: a) Immediate
Detailed Explanation:
    Immediate addressing: Operand (constant data) is embedded directly within the instruction.
Example:
    MOV AL, 25H
    Here, 25H is immediate data, not fetched from memory.
Key Point:
  →Immediate = fastest, no memory lookup.
  →Limitation = data size fixed by instruction length
Others option:
    b) Direct → instruction gives the memory address, not data itself.
    c) Register indirect → operand is inside memory, but address is in a register.
    d) Relative → used in jumps (address = PC + offset).

Answer: b) Indexed
Detailed Explanation:
    Indexed Addressing Mode:
    Effective Address = Base Address (in register) + Index/Displacement.
    Perfect for arrays → Base = array start, Index = element offset.
    Example:
    MOV AL, [BX + SI] → Access array element.
Key Point:
 Indexed addressing = designed for structured data like arrays/tables

Answer: b) JMP
Detailed Explanation:
JMP (Jump instruction):
Transfers execution to a new memory address unconditionally.
Example: JMP 2000H → control goes directly to memory location 2000H.

 Types:
       Near jump (within same segment).
       Far jump (different segment).

Others option:
    a) CMP → comparison instruction, sets flags.
    c) CALL → transfers control but also saves return address (for subroutines).
    d) RET → returns control back to caller (opposite of CALL).

Answer:  a) MOV
Detailed Explanation:
    MOV = data transfer instruction.

Examples:
    MOV AX, BX → Copy BX → AX (register to register).
    MOV AX, [5000H] → Copy contents of memory (5000H) → AX (memory to register).
    MOV [6000H], AX → Copy AX → memory (6000H).
    No change in flags (unlike ADD or CMP).

Others option:
    b) ADD → arithmetic, not transfer.
    c) JMP → program control.
    d) CMP → comparison (sets flags).

Answer:  b) To resolve forward references in labels

Detailed Explanation:

Two-pass assembler process:
Pass 1:
Scans code, builds symbol table (labels, addresses).
Cannot resolve labels used before definition (forward references).
Pass 2:
Replaces symbolic addresses with actual addresses.
Generates machine code.
 Two-pass = necessary for assembly with forward jumps/labels.

Others option:
a) Execution speed → assembler doesn’t run code, just translates.
c) Memory optimization → side benefit, but not the reason.
d) Pipelining → hardware concept, not assembly.

Answer: c) CALL saves the return address on stack, JMP does not
Detailed Explanation:
   JMP:
      Transfers control unconditionally to a new address.
      No return possible unless programmed.
   CALL:
    Pushes the current instruction pointer (return address) onto the stack.
    Jumps to subroutine.
    RET instruction later pops return address to resume execution.

 CALL + RET = structured programming.
 JMP = unconditional branch, no return

Answer: b) Overlapping fetch, decode, and execute phases
Detailed Explanation:
    Pipelining:
            While one instruction is being executed, the next can be decoded, and the next one fetched.
             Increases instruction throughput.
  Example:
    Clock cycle 1: Fetch instruction 1
    Cycle 2: Decode instr. 1, Fetch instr. 2
    Cycle 3: Execute instr. 1, Decode instr. 2, Fetch instr. 3
Others option:
    a) Multiple instructions simultaneously is more like superscalar.
    c) Splitting into threads = multithreading.
    d) Multiple CPUs = multiprocessing.
Key Point:
 Pipelining ≠ faster per instruction, but higher overall throughput

Answer: a) Microcontroller integrates CPU, RAM, ROM, I/O on a single chip

Microprocessor:
         General-purpose CPU.
         Requires external RAM, ROM, I/O chips.
         Example: Intel 8086, Pentium.
Microcontroller:
         CPU + RAM + ROM + I/O + Timers all integrated.
         Designed for embedded systems.
         Example: Intel 8051, ARM Cortex-M.

Key Point:
    Microprocessor = brain, needs support chips.
    Microcontroller = brain + memory + I/O all-in-one.

Answer:  b) 20 address lines, 1 MB memory
Explanation:
    8086 has a 20-bit address bus → 2²⁰=1,048,576 bytes = 1 MB memory space.
    Data bus = 16 bits (can read/write 2 bytes at once).
Others option:
    (a) 16 address lines → 8085, not 8086.
    (c) 24 address lines (16 MB) → 80286.
    (d) 32 address lines (4 GB) → 80386 and above.

Answer:  a) 4 (AX, BX, CX, DX)
Explanation:
    AX, BX, CX, DX → 16-bit general-purpose.
    Used for arithmetic, data transfer, loop counters (CX).
    SP, BP, SI, DI → special purpose registers.

Answer: d) Instruction Flag
Explanation:
8086 flags: CF, PF, AF, ZF, SF, OF, TF, IF, DF
Instruction Flag does not exist

Answer:  b) Generated by hardware devices
Explanation:
    Hardware interrupt: signals from devices like keyboard, timer, printer.
    Causes CPU to suspend current execution and service the interrupt.
    Example: INTR pin triggers maskable interrupt

Answer:  c) Interrupt Priority
Explanation:
    Hardware prioritization or 8259A programmable interrupt controller decides which interrupt is serviced first

Answer: b) Segmented

Explanation:

Memory divided into segments (code, data, stack, extra).
Logical address = Segment:Offset

Answer: a) 23000H
Explanation:
    Physical address= (Segment × 16) + Offset = 2000H × 10H + 3000H = 23000H
    [here, Segment= 2000H, 16=10H (in Hex), Offset =  3000H ]

Answer:  c) Base indexed
Explanation:
    Effective Address = Base Register + Index Register.
    [BX + SI] is base indexed addressing.
    Useful for accessing arrays.

Answer: b) TLB (Translation Lookaside Buffer)
Explanation:
    TLB = small cache for page table entries.
    Avoids repeated page table lookups.
    Greatly improves virtual memory performance

Answer: b) Programmable peripheral interface 

The Intel 8255A (Programmable Peripheral Interface, PPI) is a general-purpose I/O device. It is designed to interface microprocessors (like Intel 8085, 8086, etc.) with external peripherals such as keyboards, displays, ADC/DAC, printers, etc.

It provides three 8-bit parallel I/O ports:

Port A – 8-bit
Port B – 8-bit
Port C – 8-bit (can be split into two 4-bit ports: C upper & C lower)
So in total → 24 I/O lines.

These ports can be programmed to work as:

→ Input ports
→ Output ports
→ Control/handshaking lines
This flexibility makes the 8255A very popular in microcomputer systems.

→ Provides parallel I/O expansion when microprocessor I/O pins are limited.
→ Flexible → can be programmed as input/output/handshake lines.
→ Widely used in keyboards, LED displays, printers, traffic control systems, robotics.

Answer: a) Pushes data onto stack 

Stack in 8086: 
→ The stack is a reserved region of memory used for temporary storage.
→ It follows the LIFO principle (Last-In, First-Out).
→ Controlled by the Stack Segment Register (SS) and the Stack Pointer (SP).

Physical address of stack top = (SS × 16) + SP

Answer: a) Allow I/O devices to access memory without CPU intervention

Explanation:

DMA (Direct Memory Access) is a hardware feature where I/O devices can transfer data directly to/from memory without constantly involving the CPU.

This reduces CPU overhead and increases throughput.

b) → CPU instruction execution isn’t the focus.
c) → DMA doesn’t reduce memory size.
d) → Virtual memory is handled by MMU, not DMA.

Answer: b) Cycle stealing

Explanation:

Cycle stealing: DMA controller “steals” single memory cycles from the CPU to transfer data. CPU slows slightly but continues execution.

Burst mode: DMA takes full control until block transfer finishes (CPU halted during transfer).

Transparent mode: DMA only transfers data when CPU is idle.

Interrupt-driven I/O: Involves CPU intervention, not direct DMA.

Answer: d) DMA controller

Explanation:

Intel 8237 is a classic DMA controller used with 8086/8088 systems. It can manage multiple DMA channels.

a) Interrupt handling is done by 8259A.
b) Timer → 8253/8254.

c) Cache control is a CPU/memory function

Answer: c) Reduces CPU overhead during I/O transfers

Explanation:

Interrupt-driven I/O still requires CPU to move each word/byte between memory and device.

DMA automates block transfer → CPU free for computation.

a) → CPU instruction speed unchanged.

b) → DMA uses system bus.

d) → Device drivers still required for control & setup.

Answer: c) CS (Code Segment)
Segmentation in 8086

The 8086 microprocessor uses segmentation to divide memory into different logical sections. Each segment has a segment register:

CS (Code Segment Register) → Stores program instructions.

DS (Data Segment Register) → Stores general program data.

SS (Stack Segment Register) → Stores stack data (temporary variables, return addresses).

ES (Extra Segment Register) → Used for extra data, often with string operations.

Each segment can be up to 64 KB in size.

? Why CS (Code Segment)?

The Instruction Pointer (IP) always points to the next instruction to be executed.

The CPU computes the physical address of the instruction as:  Physical Address=(CS×16) +IP

This ensures that instructions are fetched from the Code Segment.

Answer: b) Displacement from segment base
 What is Segmented Memory?

In 8086, memory addressing uses segmentation:

Memory is divided into segments (Code, Data, Stack, Extra).

Each segment starts at a base address (given by segment register × 16).

Inside the segment, each byte/word is located at some offset (displacement).

So: Physical Address= (Segment Register×16) +Offset
 
What is Offset?

The offset is a 16-bit value that specifies how far (displacement) from the start of the segment the desired memory location is.

It can come from registers like IP, SP, BP, SI, DI, or directly from instruction encoding.

Example:
If CS = 2000H and IP = 3000H:

Segment base = 2000H × 10H = 20000H

Offset = 3000H

Physical Address = 20000H + 3000H = 23000H

Here, 3000H is the offset.

Why not the other options?

a) Physical address 
Offset is not the final physical address. It’s just the displacement part. Physical address = Segment base + Offset.

c) Segment base 
Segment base is given by the segment register (CS, DS, SS, ES). Offset is added to the segment base.

Answer: a) MOV AX, [2000H]
Explanation:
    MOV → data transfer.
    Memory → Register.

Answer:  b) 80286
Explanation:
80286 introduced Protected Mode, allowing:
→ Access to 16 MB memory
→ Memory protection
→ Segmentation with descriptors

Real mode: 1 MB, no protection

Answer: c) Selector
 Real Mode vs Protected Mode
  In Real Mode (8086, 8088, etc.):

Segment register (CS, DS, SS, ES) directly holds the segment base (shifted left by 4 to form base).
Physical address = (Segment × 16) + Offset.

In Protected Mode (80286 onward, used heavily in 80386/80486):

Segment registers no longer store the base directly.
Instead, a segment register contains a 16-bit selector.
The selector is an index into the Descriptor Table (GDT or LDT).
Selector = 16-bit value inside the segment register.

Answer: d) Protected mode supports memory protection

Real mode: No protection, all segments overlap freely.

Protected mode: Memory isolation, privilege levels, paging

Answer:  d) All of the above
Explanation:
A Segment Descriptor is an 8-byte (64-bit) entry in the Global Descriptor Table (GDT) or Local Descriptor Table (LDT). It defines the properties of a memory segment.
    Base address: start of segment in memory
    Limit: segment size
    Access rights: read/write, execute permissions

 Answer: a) Local Descriptor Table
Explanation:
    Each task/program can have its own LDT.
    GDT = system-wide, LDT = per-task segment descriptors.

Answer:  c) 80386
Explanation:
    VM86 mode: Run 8086 real-mode programs inside protected mode OS.
    Allows multitasking DOS apps under Windows 3.x

Answer:  b) Base + Offset from descriptor
Explanation:

In protected mode, the CPU calculates physical address as:

Selector → Descriptor → Base
Base + Offset = Linear Address
If Paging = ON → Translate Linear → Physical using page tables.
If Paging = OFF → Linear = Physical
 Unlike real mode, segment can be anywhere in memory.

Answer:  c) Page Table
Explanation:
    Paging divides memory into fixed-size pages (4 KB).
    Page table → maps virtual pages → physical frames.
    Supports virtual memory

Answer: a) Dividing memory into fixed-size blocks called pages

Explanation:

Paging divides physical memory into fixed-size blocks called frames, and logical memory into pages of the same size.
Pages are mapped to frames → eliminates external fragmentation.
 b) Segmentation → variable size, logical division.
 c, d) Not related to memory management.

Answer: b) External fragmentation
Explanation:
• Since pages and frames are fixed-size, any free frame can store any page → no gaps (external fragmentation).
• Internal fragmentation may occur if the last page is partially filled

Answer: a) Programmable parallel I/O ports
Explanation:

 Purpose of 8255A:
The 8255A is used to interface I/O devices (like keyboards, displays, printers) with a microprocessor.
It allows the CPU to read from/write to external devices efficiently.

Ports A, B, C → configurable input/output.
Mode 0 → simple I/O,
Mode 1 → handshaking,
Mode 2 → bidirectional

Answer: b) Timer/Counter
 
Explanation
1. Purpose of 8253/8254
The 8253 (and upgraded 8254) is a programmable interval timer/counter used in microprocessor systems.
It is primarily used to generate precise time delays, frequencies, or counting events.

Answer: c) Programmable Interrupt Controller (PIC)

Purpose of 8259A:
The 8259A is used to manage hardware interrupts in an orderly way for the CPU.
It allows multiple interrupting devices to share a single interrupt line to the CPU.
The chip can prioritize interrupts and mask/unmask them individually.
Supports priority levels and cascading (master/slave configuration).

Answer: b) Execution and fetching
Explanation:
    Bus Interface Unit (BIU): fetches instructions, handles address and data bus.
    Execution Unit (EU): decodes and executes instructions.
    Pipelining: Improves efficiency .