৪৯তম বিসিএস ⎯ তথ্য ও যোগাযোগ প্রযুক্তি (EEE) [ ৮৯২]

A signed negative binary number is recognized by its Most Significant Bit (MSB). In binary representation, the MSB is the leftmost bit in a number. For signed numbers, the MSB determines the sign: if the MSB is 1, the number is negative, and if it is 0, the number is positive. This is based on the two's complement method, commonly used for representing signed binary numbers.

For example, in an 8-bit system (1 byte), a number like 11111111 represents -1, while 00000001 represents +1. The MSB in these numbers indicates the sign, with 1 indicating negative and 0 indicating positive. This allows the system to distinguish between positive and negative values based on just the MSB.

The Least Significant Bit (LSB), on the other hand, represents the smallest value in the binary number and does not provide any information about the sign. Byte and Nibble refer to data size (8 bits and 4 bits, respectively) but do not directly indicate whether a number is positive or negative.

A word is a unit of data that typically represents a fixed number of bits in a computer's architecture. The number of distinct values a word can represent depends on its bit-length.

In this case, a 16-bit word can represent 16 distinct values, which is a correct interpretation. A 16-bit word can represent 2^16 distinct values, which is 65,536 possible values. However, if the question is asking about 16 distinct values, a 4-bit nibble can represent exactly 16 distinct values (2^4 = 16).

So, while a word is typically larger and can represent more values, the question likely refers to a 4-bit unit, for which the correct term would be nibble. However, if the answer provided is "word," it might be referring to a broader definition.

To convert a decimal fraction to binary, you multiply the fraction continuously by 2. After each multiplication, the integer part (before the decimal point) is noted down as part of the binary equivalent, and the process is repeated with the fractional part.

For example, to convert 0.625 to binary:

Multiply 0.625 by 2 → 1.25 (take the integer part, which is 1)
Multiply the remaining 0.25 by 2 → 0.5 (take the integer part, which is 0)
Multiply 0.5 by 2 → 1.0 (take the integer part, which is 1)
Thus, the binary equivalent of 0.625 is 0.101.

The key point is that multiplying the fraction by 2 repeatedly helps generate its binary representation.

To convert the octal number (532.2)_8 to decimal, we need to break it into two parts: the integer part (532) and the fractional part (0.2).

Converting the integer part 532 from octal to decimal:

Each digit in an octal number is multiplied by 8 raised to the power of its position, starting from 0 from the right.

532₈ = 5 × 8² + 3 × 8¹ + 2 × 8⁰
 = 5 × 64 + 3 × 8 + 2 × 1
 = 320 + 24 + 2
 = 346

Converting the fractional part 0.2 from octal to decimal:

Each digit in the fractional part is multiplied by 8 raised to the negative power of its position.

0.2₈ = 2 × 8^(-1) = 2 × (1/8) = 0.25

Combining both parts:
532.2₈ = 346 + 0.25 = 346.25₁₀

Thus, the decimal equivalent of (532.2)₈ is (346.25)₁₀.

So the correct answer is (ক) (346.25)₁₀.

To convert the binary number (1011.011)_2 to decimal, we need to break it into two parts: the integer part (1011) and the fractional part (.011).

Converting the integer part 1011 from binary to decimal:

Each digit in a binary number is multiplied by 2 raised to the power of its position, starting from 0 from the right.

(1011)₂ = 1 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰
     = 1 × 8 + 0 × 4 + 1 × 2 + 1 × 1
     = 8 + 0 + 2 + 1
     = 11

Converting the fractional part .011 from binary to decimal:

Each digit in the fractional part is multiplied by 2 raised to the negative power of its position.

(0.011)₂ = 0 × 2^(-1) + 1 × 2^(-2) + 1 × 2^(-3)
        = 0 × 0.5 + 1 × 0.25 + 1 × 0.125
        = 0 + 0.25 + 0.125
        = 0.375

Combining both parts:
1011.011₂ = 11 + 0.375 = 11.375₁₀

Thus, the decimal equivalent of (1011.011)₂ is (11.375)₁₀.

The correct answer is (ক) (11.375)₁₀.

The binary system uses only two digits, 1 and 0, to represent all numbers. To represent larger decimal numbers in binary, the string of 1's and 0's tends to become quite long. This is because the binary system grows exponentially in terms of the number of digits needed to represent a number as it increases.

For example:

The decimal number 10 is represented as 1010 in binary (4 digits).
The decimal number 1000 requires 1111101000 (10 digits).
Thus, as the decimal number increases, the binary representation grows larger, requiring a significant number of binary digits (1's and 0's). This is considered a drawback compared to other systems like hexadecimal, which use more digits to represent larger numbers in a more compact form.

To convert the octal number (645)_8 to decimal, we need to break it into its integer parts and use the powers of 8.

Converting the octal number 645 to decimal:

Each digit in an octal number is multiplied by 8 raised to the power of its position, starting from 0 from the right.

645_8 = 6 × 8^2 + 4 × 8^1 + 5 × 8^0
     = 6 × 64 + 4 × 8 + 5 × 1
     = 384 + 32 + 5
     = 421

Thus, the decimal equivalent of (645)_8 is (421)_10.

In the hexadecimal number system, digits range from 0 to 9 and then A to F, where:

A = 10, B = 11, C = 12, D = 13, E = 14, and F = 15.
The largest possible two-digit hexadecimal number is FF, where both digits are F (the maximum value of a single digit in the hexadecimal system).

A double word typically refers to a data size of 32 bits in most computer architectures. It is called a "double" word because it is twice the size of a standard word, which is usually 16 bits. Therefore, a double word is 32 bits or 4 bytes.

In Boolean algebra, the OR operation follows the properties of:

Associative property: This states that the grouping of operands does not affect the result of the OR operation.

A+(B+C)=(A+B)+C
Commutative property: This states that the order of operands does not affect the result of the OR operation.

A+B=B+A
Distributive property: This states that OR distributes over AND (just like multiplication distributes over addition in arithmetic).

A+(B⋅C)=(A+B)⋅(A+C)
Thus, the OR operation in Boolean algebra satisfies all of the mentioned properties.
 
 
 

The expression A(A + B) simplifies using Boolean algebra rules:

Distributive property: We can distribute A over (A + B).

A(A+B)=A⋅A+A⋅B=
Idempotent law: Since A \cdot A = A, the expression becomes:

A+A⋅B=
Absorption law: The A term absorbs A \cdot B because A + A \cdot B = A.
Thus, the simplified result is A.

To find the complement of the Boolean expression A'B + CD', we apply De Morgan's Theorem.

The original expression is:
A'B + CD'

Now, apply the complement to the entire expression:
(A'B + CD')'

By De Morgan's law, this becomes:
(A'B)' . (CD')'

Now, apply De Morgan's law again to each part:

- (A'B)' = A + B'
- (CD')' = C' + D

Thus, the complement of the original expression is:
(A + B')(C' + D)

Since B' is the complement of B, the final answer is:
(A + B)(C' + D)

We are given the Boolean expression:

Y = AB' + (A' + B)C

 Distribute the C over the terms inside the parentheses:
Y = AB' + A'C + BC

Simplify using combination and absorption laws:
- The term AB' cannot combine with A'C or BC directly, but we can combine AB' and A'C using the absorption law:
AB' + A'C = AB + A'

The simplified expression is:
Y = AB + A'

A Karnaugh map (K-map) is an abstract form of a Venn diagram. It is a tool used in Boolean algebra for simplifying Boolean expressions. The K-map represents the truth table of a Boolean function in a matrix form, where each square represents a combination of variable values.

A Venn diagram, on the other hand, is a visual representation of sets, and the K-map is closely related to Venn diagrams because both help in visualizing combinations of variables and their relationships.

A Karnaugh map (K-map) for n variables has 2ⁿ cells. For a 4-variable K-map, the number of cells is:

2⁴ = 16
So, there are 16 cells in a 4-variable K-map.

An S-R (Set-Reset) flip-flop is a basic type of flip-flop that has two inputs: S (Set) and R (Reset). The flip-flop also has two outputs: Q and Q'.

The truth table for an S-R flip-flop includes the following states:

S = 0, R = 0: This state retains the current output (no change).
S = 1, R = 0: This sets the output Q = 1.
S = 0, R = 1: This resets the output Q = 0.
S = 1, R = 1: This is an invalid state because it leads to an undefined or conflicting output.
Therefore, the truth table has 3 valid entries (when S = 0, R = 0; S = 1, R = 0; S = 0, R = 1).

A J-K flip-flop is a type of flip-flop with two inputs: J and K. The behavior of the flip-flop is as follows:

When J = 0 and K = 0, the output Q does not change (it holds the previous state).
When J = 0 and K = 1, the output Q is reset to 0.
When J = 1 and K = 0, the output Q is set to 1.
When J = 1 and K = 1, the output Q toggles, i.e., it changes from 0 to 1 or from 1 to 0.
So, when both inputs J and K are 1, the output will toggle.

A gated D-type flip-flop is a type of flip-flop that has a D input, a clock input, and a gate input. The behavior of the gated D-type flip-flop is as follows:

The Q output follows the D input when the enable (gate) input is HIGH and the clock input triggers a change.
The output complement Q' follows the D input as well, when the flip-flop is enabled and the clock is activated.
Let's break down the options:

(ক) "The Q output is either SET or RESET as soon as the D input goes HIGH or LOW" – This is not correct, because the output change only occurs at the clock edge when the enable is HIGH.

(খ) "The output complement follows the input when enabled" – This is the correct description of the gated D flip-flop. When enabled, the output and its complement follow the D input.

(গ) "Only one of the input can be HIGH at a time" – This is incorrect. Both inputs can be HIGH in some configurations, depending on the flip-flop's design.

(ঘ) "The output toggles if one of the input is held HIGH" – This is incorrect for a gated D flip-flop. A toggling behavior is typically associated with T-type flip-flops.

A basic S-R flip-flop (Set-Reset flip-flop) can be constructed by cross-coupling two NOR gates or two NAND gates. These gates form the core of the flip-flop’s feedback mechanism, which determines its state.

NOR gates: When two NOR gates are cross-coupled, they create a stable state where the output can either be set (1) or reset (0), depending on the inputs (S and R). This configuration is often referred to as the NOR-based SR flip-flop.
NAND gates: Similarly, two NAND gates can also be cross-coupled to form a stable SR flip-flop, known as the NAND-based SR flip-flop.
Both configurations enable the flip-flop to store a bit of data, and the inputs S (Set) and R (Reset) control the state changes.

Combinational circuits: These circuits produce an output based purely on the current inputs, without any memory of past states.
Sequential circuits: These circuits have memory elements that store past states. Their output depends not only on the present inputs but also on the past outputs. These circuits use feedback loops, and examples include flip-flops and latches.
Latches: Latches are a type of memory element used in sequential circuits. They store a single bit of data and are level-sensitive (they change their state based on the level of the clock signal).
Flip-flops: Flip-flops are a more advanced form of memory elements used in sequential circuits. They are edge-triggered, meaning they change their state based on the edge (rising or falling) of a clock signal.

Combinational circuits: These circuits perform operations where the output depends solely on the current inputs, without any memory elements. As there are no feedback loops or dependence on past states, combinational circuits generally have faster operations compared to sequential circuits, latches, and flip-flops.
Sequential circuits: These circuits depend on both current inputs and past outputs, incorporating memory elements such as flip-flops or latches. The need to store and update past states typically makes sequential circuits slower than combinational circuits.
Latches and Flip-flops: Both are types of memory elements used in sequential circuits. Latches are level-sensitive and typically have faster response times than flip-flops, but flip-flops are edge-triggered and are more commonly used in synchronous systems. However, both involve some form of memory, which makes their operations slower than pure combinational circuits.

A basic latch is a simple memory element that stores a bit of information. It typically consists of two inverters connected in a feedback loop, forming a bistable circuit. This configuration allows the latch to maintain a stable state until it is changed by an input signal.

Two inverters: The inverters form the core of a latch, creating two states (set and reset). When the latch is enabled, it can either store a 1 or a 0, depending on the input.
Two amplifiers, two comparators, and two adders are not typically part of a basic latch. These components are used in different types of circuits, such as amplifiers in analog circuits, comparators in comparison operations, and adders in arithmetic operations.

In an S-R flip-flop, the output Q represents the stored state. When Q = 0, it indicates that the flip-flop has been reset. The reset operation is achieved when the R (reset) input is activated, causing the output Q to become 0, while the complementary output Q' becomes 1.

Set occurs when Q = 1 and the S (set) input is activated.
Previous state refers to the state the flip-flop was in before any input was applied, which is not directly indicated by Q = 0.
Current state could be Q = 0 or Q = 1, depending on the present input, but the correct term for Q = 0 specifically is reset.

A NOR-based S-R latch is classified as an asynchronous sequential circuit because of its cross-coupled connection. In this circuit, two NOR gates are cross-coupled to form a feedback loop. This means that the output of each NOR gate is fed back into the input of the other, allowing the circuit to store its state and react to changes in the inputs without needing a clock signal.

Asynchronous: The latch operates without needing a clock signal, meaning it can change its state at any time based on the inputs.
Cross-coupled connection: The two NOR gates in the latch are connected in a way that they depend on each other's output, which is key to the latch's functionality.
Thus, the classification as an asynchronous sequential circuit comes from the feedback loop (cross-coupled connection) that enables the circuit to store and change its state based on input signals, without requiring synchronization through a clock signal.

The main difference between a register and a counter lies in their functions:

Register: A register is a memory storage element used to store binary data. Registers can store multiple bits of information, but they do not operate in any specific sequence or perform counting operations. Their role is to hold data temporarily for processing or for transfer between circuits.
Counter: A counter, on the other hand, is a sequential circuit that counts in a specific sequence (usually in binary). It typically increments or decrements based on clock signals and has a predefined sequence of states. Counters are often used for counting events or generating specific timing sequences.

A data register is a register used to store binary information temporarily for processing. It holds the data that is being transferred between different parts of a computer system, such as between the CPU and memory, or between different CPU components.

Let's break down the other options:

Binary register: While it could be a general term, it is not commonly used to describe a register specifically meant for storing data in a binary format.
Shift register: A shift register is a type of register used to shift data bits in a particular direction (left or right) for operations like data serialization or parallel-to-serial conversion.
D-register: A D-register is a type of flip-flop that stores a single bit of data, often used in sequential circuits, but it is not used as a general-purpose data register for storing multi-bit binary information.

A counter circuit is typically constructed using flip-flops connected in cascade (also called "serially"). Flip-flops are sequential logic circuits that store individual bits of data, and by connecting multiple flip-flops in cascade, we can create a counter that counts in binary or other specific sequences (e.g., up or down).

Each flip-flop stores one bit of information, and when combined in cascade, the flip-flops form a counter capable of representing multiple bits (n-bits). A common example of such counters is the binary counter, where the state of each flip-flop corresponds to a bit of the binary count.

In a computer system, the instructions that are executed by the processor are stored in memory. Memory holds both the program code (instructions) and data that the CPU needs to process. The CPU fetches instructions from memory, decodes them, and executes them.

CPU: The CPU (Central Processing Unit) is responsible for executing instructions, but it does not store the instructions itself. It fetches them from memory.
Control unit: The control unit is a part of the CPU that coordinates the operations by directing the flow of data between the CPU and other components. It does not store the instructions.
Microprocessor: A microprocessor is a type of CPU, and like the CPU, it executes instructions but does not directly store them. The instructions are fetched from memory.

Statistical Time-Division Multiplexing (TDM) is a method of multiplexing where time slots are dynamically allocated to active input lines, unlike synchronous TDM where time slots are fixed and pre-allocated even if there is no data to send [1.1]. This dynamic allocation makes Statistical TDM more efficient in utilizing bandwidth, especially in handling bursty or variable bit rate traffic, as it prevents the waste of unused time slots [1.1]. Due to this characteristic of not relying on fixed, synchronized time slots, Statistical TDM is also known as Asynchronous TDM [1.1]. It is sometimes also referred to as Intelligent TDM

The message source in a communication system is responsible for generating the data that needs to be transmitted, such as text, audio, or video. This data is then converted into an appropriate signal for transmission.

Transmission media refers to the physical medium (such as copper wires, fiber optics, or wireless airwaves) that carries the encoded signal from the sender to the receiver in a communication system.

Fiber optic cables offer the highest bandwidth compared to other transmission media, allowing for the transmission of large amounts of data over long distances with minimal loss and interference.

Signal-to-noise ratio (SNR) is a measure of the strength of the signal relative to the background noise. A higher SNR indicates better signal quality, as the signal is stronger compared to the noise.

The formula to calculate the Signal-to-Noise Ratio (SNR) in decibels (dB) is:

SNR (dB)=10×log_⁡10(Psignal/Pnoise)
Where:

P_signal is the signal power (in mW),
P_noise​ is the noise power (in mW).
Given:

P_signal=100 mWP
P_noise=10 mWP
Substitute the values into the formula:

SNR (dB) = 10×log⁡₁₀(100/10)
SNR (dB) = 10×log₁₀​(10)
= 10×1 = 10dB

Explanation: The frequency components of AM waves are: Carrier frequency (ω_c) with amplitude A, Lower sideband (ωc – ωm) having amplitude mA/2 and Upper side band (ω_c + ω_m) having amplitude ^mA ⁄2 (where m represents modulation index, A is the amplitude of the carrier signal, ω_m is the amplitude of the message signal).

 Time Division Multiplexing is used to transmit digital signals. FDM and WDM techniques are used to transfer analog signals. WDM (Wave Division Multiplexing) is partly similar to FDM (Frequency Division Multiplexing). FDM is used for signal transmission through a twisted-pair cable while WDM is used to transmit signals through optical fiber cables.

 We know, Modulation Index(µ) = (Vmax-Vmin)/(Vmax+Vmin),
Where, Vmax = Maximum Amplitude of an amplitude modulated = 10V
Vmin = Minimum amplitude of an amplitude modulated = 5V
Therefore, µ = (10-5)/(10+5) = 0.33.

In low-level modulation, the generation of amplitude modulated signal takes place at low power levels. The generated AM signal is then amplified using a chain of linear amplifiers, which are required to avoid waveform distortion. Thus, linear amplified modulated stage is used in low level amplitude modulated system.

According to Carson’s rule, the required bandwidth is twice the sum of the maximum frequency deviation and the maximum modulating signal frequency or B = 2(f_d + f_m)Hz.

Amplitude modulation is the change in the amplitude of carrier wave in proportion to the instantaneous amplitude of the message signal. A carrier can be seen as a waveform with frequency higher than the message signal frequency, that is modulated with respect to input signal for the purpose of transmitting information. The equation for full-carrier AM is V(t) = (E_c + E_m sin⁡ω_m t) × (sin ⁡ω_c t).

Single side band suppresses the carrier and uses only one of the two sidebands. The two sidebands carry exactly the same information and thus removing a sideband does not have any effect on the signal. To demodulate upper sideband of signal it is necessary that the receiver must be set to USB mode and have the ability to reinsert the carrier.

Rectangular waveguides are the earliest form of transmission lines. It supports TM and TE mode, which stands for Transverse Magnetic waves and Transverse Electric waves respectively, but it does not support TEM, Transverse Electromagnetic waves, mode. A rectangular waveguide can’t propagate below some certain frequency. The dominant mode for it is TE 10 mode.

The Sampling Theorem states that the signal must be sampled at a frequency that is at least twice the maximum frequency component of the signal to prevent aliasing: fs​≥2fm​.

The bandwidth of a PAM signal is typically twice the bandwidth of the original signal, since each pulse may represent multiple samples. Hence, the required bandwidth for the PAM signal would be:
Bandwidth_PAM​=2×Bandwidth_signal​=2×5kHz=10kHz

The Signal-to-Quantization Noise Ratio (SQNR) for a uniform quantizer can be approximated by the formula:
SQNR (dB)=6.02N+1.76
Given:
N=8 bits

SQNR (dB) = 6.02 × 8 + 1.76
= 48.16 + 1.76
= 49.92dB
≈ 50dB

The quantization step size Δ for PCM is given by:
Δ=A​/2<sup>N

Where:</sup>
A=10V is the peak-to-peak amplitude,
N=4 is the number of bits.

Δ=10/2⁴​=0.625V

For FSK, the bandwidth BFSKB_{\text{FSK}}BFSK​ is approximated by:
B_FSK​≈R_b​+Δf
Given:
R_b​ = 1Mbps
Δf = 100kHz

The required bandwidth is:
B_{FSK ​}≈ 1MHz + 0.1MHz = 1.1MHz

Larger the number of discrete amplitudes, finer will be the quantization.

a low-pass filter is a standard method for detecting or demodulating a Pulse Amplitude Modulation (PAM) signal, as it effectively removes the high-frequency carrier ripple and reconstructs the original modulating message signal. By setting the filter's cutoff frequency appropriately (just above the highest frequency of the message signal but below the sampling frequency), it can isolate the desired information from the pulse train.   
 PAM Signal Input: A PAM signal consists of a series of pulses whose amplitudes vary according to the original message signal.  
Filtering: When this signal is passed through a low-pass filter, the filter's function is to:

1. Remove High-Frequency Components: The pulses in the PAM signal introduce high-frequency ripple and sidebands due to the sampling process. The low-pass filter attenuates these unwanted high-frequency components. 
2. Isolate the Message Signal: The filter's cutoff frequency is set to be just above the highest frequency component of the original message signal (fₘ). This allows the filter to pass the low-frequency information of the message signal while blocking the higher frequencies associated with the carrier pulses. 

Signal Reconstruction:  The output of the low-pass filter is a continuous signal that approximates the original message signal before it was sampled. This process essentially "smoothes out" the pulsed signal to recover the analog message. 

Frequency-Division Multiple Access (FDMA) uses frequency division to allocate separate frequency bands to different users. Each user is assigned a different frequency for communication.