৪৯তম বিসিএস ⎯ কম্পিউটার সায়েন্স (CSE) [৯৭১] · তারিখ অনির্ধারিত · ২৯ প্রশ্ন
Though there are various types of gates including AND, OR, NOT, NAND, NOR etc.. NAND and NOR gates are a little special. NAND gate and NOR gate can be termed as universal logic gates since any arbitrary Boolean function can be implemented using NAND gate or NOR gate only.
Here AND, OR and NOT gates are Basic Gates.
Boolean Function of Ex-OR gate = A'B+AB'
Output Function of Ex-OR = A'.B + A.B' (for input A and B)
Then Output of 1st Ex-OR = 1'.X + 1. X' (for input 1 and X)
= 0 + X' = X' (here 1' = 0)
Output of 2nd Ex-OR = X'. X' + (X')'. X (for input X' and X)
= X' + X.X
= X' + X
= 1 ( A' + A = 1)
for 3rd Ex-OR input as same as First gate(1 and X) So Output of 3rd Ex-OR will be X'
Thus.. 4th Ex-OR input as same as 2nd gate(X' and X) So Output of 3rd Ex-OR will be 1
Therefore,
Output value of gate of Even Numbered will be 1
Output value of gate of Odd Numbered will be X'
So, Output Of Y(20th Numbered) = 1
Here Sum= ((A.(A.B)')'. (B.(A.B)')')'
= (A.(A.B)')''+ (B.(A.B)')'' (Using De Morgens)
=A.(A.B)' + B.(A.B)' = A(A'+B') + B(A'+B')= AA'+ AB'+ BA'+BB'=AB'+A'B
Carry= (A.B)''=A.B
SOP for Output Sum= A'B'C+ A'BC'+ AB'C'+ ABC
Answer: 2
A combinational circuit produces an output based on input variables only, but a sequential circuit produces an output based on Present input and previous output states.
Flip-flops are the fundamental building blocks of memory in digital circuits. Each flip-flop stores one bit and is used in devices like registers, counters, and memory units.
A flip-flop is a bistable device (has two stable states: 0 and 1) and is used to store a single bit of digital information.
In synchronous sequential circuits, all state transitions are controlled by a common clock signal. This synchronizes changes across all memory elements Like Flip flops.
Where asynchronous sequential circuits state transitions are controlled by enable signal like Latch.
In an SR (Set-Reset) flip-flop, when S = 1 and R = 1, both outputs Q and Q' try to go to 0, which is invalid (Q = Q'). This state is undefined or indeterminate, and is avoided in proper design.
Explanation: For JK flip-flop: J = 0, K = 1 ⇒ Reset the output (Q = 0). It behaves similarly to an SR flip-flop but without the invalid state.
Explanation: Edge-triggered flip-flops respond only to the transition (edge) of the clock signal — either from 0 to 1 (rising edge) or 1 to 0 (falling edge), making their behavior predictable.
The JK flip-flop is essentially an enhanced SR flip-flop where the undefined condition (J = 1, K = 1) is replaced with a toggle operation,
solving the indeterminate issue.
SR Flip-Flop:
The SR (Set-Reset) flip-flop has two inputs: S (Set) and R (Reset).
When S = 1 and R = 0, the output is set (Q = 1).
When S = 0 and R = 1, the output is reset (Q = 0).
However, when S = 1 and R = 1, the output is indeterminate (undefined), because both outputs (Q and Q') would try to go to the same state, leading to a conflict (Q = Q').
JK Flip-Flop: Like SR flip- flop other than the JK flip-flop solves this issue by replacing the invalid condition (S = 1 and R = 1) with a toggle behavior.
Explanation: If J = 1, K = 1, the JK flip-flop toggles.
Current output = 0 ⇒ Next output = 1
The D flip-flop is the most suitable flip-flop for storing data, and it is commonly used in registers, counters, and memory units where data needs to be stored reliably and transferred in synchronization with a clock.
flip-flop uses:
Explanation: In a T (Toggle) flip-flop:
T = 1 ⇒ Output toggles
T = 0 ⇒ Output remains unchanged
A D flip-flop can be created from a JK flip-flop by connecting an inverter between the J and K inputs and connecting the D input to the J input. This configuration effectively forces the JK flip-flop to behave like a D flip-flop. When D is high (1), the J input becomes 1 and the K input becomes 0, setting the flip-flop. Conversely, when D is low (0), the J input becomes 0 and the K input becomes 1, resetting the flip-flop.
Here, J=D
K=D'
SO, J=K'
To convert a JK flip-flop into a T flip-flop, simply connect the J and K inputs of the JK flip-flop to a single input, labeled 'T'. When T is 0, the flip-flop retains its previous state. When T is 1, the flip-flop toggles to the opposite state.
Here,
T=J
T=K
So, J=K
JK flip-flop is a versatile and more reliable flip-flop
No undefined state: The JK flip-flop avoids the indeterminate or invalid state that exists in the SR flip-flop when both inputs are 1.
Versatility: It can be used as a SR flip-flop, T flip-flop, or D flip-flop depending on how the inputs are connected. Specifically:
If J = S and K = R, it behaves like an SR flip-flop.
If J = 1, K = 1 for each clock pulse, it behaves like a T flip-flop (toggle mode).
If J = D and K = D' (inverted), it can be configured as a D flip-flop.
Thus, the JK flip-flop is a versatile and more reliable flip-flop
Each flip-flop in a register can store one bit of data. Therefore, n flip-flops can store n bits.
Explanation: A D flip-flop is the most common building block of registers used to store 1-bit data. A register is typically a collection of D flip-flops, with each flip-flop storing one bit of data.
Explanation: A mod-16 counter will count from 0 to 15 (16 states in total). The modulus of a counter represents the number of distinct states it can go through before resetting to 0.
Explanation: An Up counter increments its output by 1 on each clock pulse.
For example, a 4-bit up counter counts from 0000 (0) to 1111 (15) in binary.
Concept:
For an 'n' flip flop counter,
• The total number of states = 2n (0 to 2n-1)
• The largest number that can be stored in the counter = 2n-1
To construct any mod counter, the minimum number flip flops required such that: Modulus ≤ 2 Where n is the number of counters.
Calculation:
Number no. of flip-flops are required to construct a mod-200 counter is obtained as:
2n ≥ 200
For n = 8
28 = 256 > 200
∴ 8 flip-flops required to construct a counter to count upto 200 (decimal)